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International
Semiconductor Technologies
SC11210 Data
Sheet

Caller Identification Circuit
CONTENTS
Features
General
Description
Block
Diagram
Pin
Description
Circuit
Description
Functional
Description
Terms
Of Sale
Dowmload
Datasheet

FEATURES
TOP

8 pin PDIP Version for Small Size

Power Down Circuitry

Selectable Energy Detection

Energy Detection can be used as Call Progress Filter

FSK Demodulator

GENERAL
DESCRIPTION
TOP
The
SC11210 and SC11211 are analog front ends which can be used to
support the Caller Number Delivery (CND) feature in a General
Switched Telephone Network (GSTN). This service is provided by
the telephone company and is intended for residential and
business telephone customers. It allows called customers to
receive a calling party's number during the ringing cycle. The
data corresponding to the caller number is transmitted to the
customer premises when the telephone is on-hook and a voice
path has been established. If power ringing is used to
establish the voice path, then data transmission occurs during
the silent interval between the first and second power ringing
signal. IST's SC11210 and SC11211 are designed to interface to
the signaling scheme that is shown in Table 1.

Link Type

Simplex, two wire

Transmission Scheme

Analog, phase-coherent frequency shift
keying (FSK)

Logical 1 (Mark)

1200 ± 12Hz

Logical 0 (Space)

2200 ± 22 Hz

Transmission Rate

1200 bps

Application of Data

Serial,Binary, Asynchronous

Transmission Level

-13.5 ± 1 dBm at the point of data
application into a resistive load of 900 ohm

Insertion Loss @ 3KHz

10-14dB

Table
1. Caller I.D. Signaling Scheme

BLOCK
DIAGRAM
TOP

PIN
DESCRIPTIONS
TOP
The
chip is available in a 8 or 14 pin package. Only the 14 pin
version supports the power-down and call progress detect
function and has four energy detect levels. The following is a
description of the pins.

PIN NAME

PIN NO.

SC11210

P1

PIN NO.

SC11211

P2,P3

DESCRIPTION

CPM

13

Call progress control pin. When pulled low
the input band pass filter shifts center frequency and
bandwidth

DO

7

12

The output of the FSK demodulator appears
at this pin

ED

6

11

Energy- Detect output. Goes low when in
band energy is present and detected by the energy detect
circuit.

EDC

3

5

Energy-Detect Capacitor. A 0.1µF capacitor
should be connected between this pin and
ground.

EDLVL1

3

Energy detect level control
one.

EDLVL2

4

Energy detect level control
two.

GND

4

7

Ground pin (0V).

PD

10

Power-down pin. When pulled low the chip
will enter a sleep mode to reduce power
consumption.

VCC

8

14

Positive power supply pin(4.5-5.5
Volts).

VINN

1

1

Negative input of differential input
buffer.

VINP

2

2

Positive input of differential input
buffer.

VREF

6

Reference ground pin. For improved
performance a 1 µ F capacitor should be connected
between this pin and ground. This voltage is nominally
halfway between the positive and ground.

XTALIN

5

8

The Input pin of the
Oscillator.

XTALOUT

9

The Output pin of the
Oscillator.

NOTE: P1 is the 8
pin dip, P2 is the 14 pin dip, P3 is the 14 pin SOIC.

CIRCUIT
DESCRIPTION                                                                              TOP
The
Caller Identification Circuit is a CMOS device that operates
with a single power supply over a range of 4.5-5.5 Volts. A
block diagram of the chip is shown in Figure1. It consists of
an input differential buffer, a 4-pole band pass filter, an
FSK demodulator, a user selectable energy detect circuit, a
clock generator , and a power down feature. The frequency
response for the band pass filter is shown in Figures 3a and
3b. In a typical application, the circuit accepts the incoming
FSK signals through the differential input buffer, which in
turn is passed through the 4 pole band pass
filter.  Depending on the setting of the energy
detect pins (see Table1 ), ED will go low when enough in-band
energy is present or high when the energy level of the signal
is insufficient. The chip accepts a 3.5795454 MHz clock or a
crystal (see Figure4) and uses it to generate timing for the
internal blocks. The chip has a power-down mode which is
controlled by the PD pin. When this pin is pulled low the
power-down feature is activated. The device is available in an
8 or 14 pin package. The 8 pin version has one energy detect
level and does not support the call progress detection
function and the power down feature.

Analog Input Section
The Analog input section
accepts a differential signal which should be AC coupled to
the VINN and VINP pins. Since the chip
operates with a single power supply, an analog reference
ground is generated internally which is nominally halfway
between the positive supply and ground. To preserve
approximately the same internal and external DC levels, the
circuit of Figure 2 should be used for AC coupling the
differential signal to the input pins.

Energy Detect Circuit
The energy detect circuit
takes its input from the output of the band pass filter. It
rectifies the signal and uses an averaging circuit to
determine the energy level. It needs an external capacitor for
its operation. With the external capacitor equal to 0.1µF,the
on-to-off and off-to-on response times of the energy detect
will nominally be 5ms. The energy detect level has four
distinct values and is controlled by the two EDLVL1 and EDLVL2
pins according to the listing in Table 2.

These levels are valid for the positive power supply equal
to 5V DC. In the 8 pin package the EDLVL1 and EDLVL2 pins are
not available and they are held low with internal pull downs.
Therefore in the 8 pin package the only available energy
detect level is -30 dBm.

Power-Down Mode
In the 14 pin package the PD pin
controls the power-down function. When this pin is pulled low
the chip will be power-downed and the supply current will
reach to its minimum level and the oscillator is inactive. In
the 8 pin package this pin is not available and it is held
high with an internal pull up.

EDLVL2

EDLVL1

DETECT LEVEL 1

0(open)

0 (open)

-30 dBm on -35 dBm off

0(open)

1

-27 dBm on -32 dBm off

1

0(open)

-24 dBm on -29 dBm off

1

1

-21dBm on -26 dBm
off

Note 1: dBm=decibels above
or below of reference power of 1 mW into a 600 Ohm load.

Table 2. Energy detection levels

FUNCTIONAL
DESCRIPTION                                                                      TOP
Absolute
Maximum Ratings
Operating
Conditions
DC
Electrical Characteristics
AC
Characteristics
Physical
Dimensions

ABSOLUTE MAXIMUM RATINGS (Notes 1,2,
&
3)                                  TOP                      BACK

Supply Voltage, Vcc - GND

+ 6V

Voltage on any Pin

GND - 0.3 to Vcc + 0.3 V

Current on any Pin

10 mA

Storage Temperature

-65 oC to + 150
oC

Power Dissipation (Note3)

100 mW

Lead Temperature (Soldering 10sec)

300
oC

OPERATING CONDITIONS
(Note4)                                                            TOP                      BACK

PARAMETER

DESCRIPTION

CONDITIONS

MIN

TYP

MAX

UNITS

TA

Ambient Temperature

0

70

oC

VCC

Positive Supply Voltage

4.5

5.0

5.5

V

GND

Ground

0

V

FC

Crystal Frequency

3.576

3.579545

3.583

MHz

NOTE 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur.

NOTE 2: Unless
otherwise specified all voltages are referenced to
ground.

NOTE 3: Power dissipation temperature
derating:
Plastic package: -12mW/C from 65 oC to 85
oC

Ceramic package: -12mW/C from 100 oC to 125
oC

NOTE 4: Min and max
values are valid over the full temperature and operating
voltage range. Typical values are for 25 oC and 5 V
operations.

DC ELECTRICAL CHARACTERISTICS (Notes 1
and
2)                            TOP                      BACK

SUPPLY

PARAMETER

DESCRIPTION

CONDITIONS

MIN

TYP

MAX

UNITS

VCC

Operating Supply Voltage

4.5

5.5

V

ICC

Operating Supply Current

7

mA

PO

Power Consumption PD=1

f=3.579MHz;
VCC=5V

35

mW

PD

Power Consumption PD=0

15

µA

INPUTS

PARAMETER

DESCRIPTION

CONDITIONS

MIN

TYP

MAX

UNITS

VIL

Low Level Input Voltage

.8

V

VIH

High Level Input Voltage

2

V

IIH/IIL

Input Leakage Current

VIN=GND or
VCC

0.1

µA

PD

Pull Up(Source)Current

100

µA

EDLVL

Pull Down(Sink)Current

100

µA

CLKIN

Load Capacitance

20

pF

CLKIN

High Level Input Leakage Current

3

50

µA

CLKIN

Low Level Input Leakage Current

3

50

µA

OUTPUTS

PARAMETER

DESCRIPTION

CONDITIONS

MIN

TYP

MAX

UNITS

IOL

Output Low(Sink) Current

VOUT=0.4V

1.0

2.5

mA

IOH

Output High (Source)Current

VOUT=4.6V

0.4

0.8

mA

CLKOUT

Driving Capacitance

100

µA

CLKOUT

High Level

VOUT=2.8V

200

µA

CLKOUT

Low Level

VOUT=0.4V

20

pF

NOTE
1: Absolute maximum ratings are those values beyond which
damage to the device may occur.

NOTE 2: Unless
otherwise specified all voltages are referenced to ground.

AC
CHARACTERISTICS                                                                               TOP                      BACK

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNITS

VINTto GND
VINR to GND

Impedance (PD=1)
Impedance (PD=0)

75

100
3.3

125

kohm
kohm

VINT to
VINR

Impedance (PD=1)
Impedance (PD=0)

150

200
6.6

250

kohm
kohm

VINT
VINR

Differential Voltage on High Input Imp.
(PD=1)

24.5

mV1

VINT
VINR

Differential Input Level into 600 ohm
(PD=1)

-30

dBm1

VINT
VINR

Voltage on either tip or ring (14 to 65 Hz
) (PD=0)

600

mVRMS

NOTE 1: Maximum Differential Input Voltage Peak
to Peak: 0.75 V

PHYSICAL
DIMENSIONS                         TOP                      BACK

8-Lead
Moulded DIP
14-Lead
SOIC
14-Lead
Moulded DIP

Package 8-Lead Moulded
DIP                   TOP                      BACK

Package 14-Lead
SOIC                                       TOP                      BACK

Package 14-Lead Moulded
DIP                             TOP                      BACK

TERMS OF
SALES                                                                                                     TOP
Devices
sold by International Semiconductor Technologies(IST) are
covered by the warranty and patent indemnication provisions
appearing in the Terms of sale only. IST makes no
warranty,express, statutory, implied or by description
regarding the information set forth herein or regarding the
freedom of the described devices form patent infringement. IST
makes no warranty of merchantability or fitness of any
purpose. IST reserves the right to discontinue production and
change any specifications and prices at any time and without
notice.

The product is intended for use in normal commercial
applications. Applications requiring an extended temperature
range, unusual environmental requirements or high reliability
applications,such as specifically not recommended without
additional processing by IST.

IST assumes no responsibility for the use of any circuitry
other than circuitry embodied in IST product. No other
circuits,patents,licenses are implied.

LIFE SUPPORT POLICY
IST products are not
authorized for use as critical components in life support
devices or systems.

Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life,and whose failure to
perform,when properly used in accordance with instruction
for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.

A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system,or to effect its safety or effectiveness.

© 1997
INTERNATIONAL SEMICONDUCTOR TECHNOLOGIES
Tel 650-947-9844,  Fax 650-618-1553
Internet : http://www.ist.com

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